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LTC4300A-3 Level Shifting Hot Swappable 2-Wire Bus Buffer with Enable
FEATURES
s s
DESCRIPTIO
s s s
s s
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Bidirectional Buffer* for SDA and SCL Lines Increases Fanout Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane Logic Threshold ENABLE Input Isolates Input SDA and SCL Lines from Output Compatible with I2CTM, I2C Fast Mode and SMBus Standards (Up to 400kHz Operation) 1V Precharge on all SDA and SCL Lines Supports Clock Stretching, Arbitration and Synchronization 5V to 3.3V Level Translation High Impedance SDA, SCL Pins for VCC = 0V, VCC2 = 0V Small 8-Pin DFN and MSOP Packages
The LTC(R)4300A-3 hot swappable 2-wire bus buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. When the connection is made, the LTC4300A-3 provides bidirectional buffering, keeping the backplane and card capacitances isolated. Rise-time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise-time requirements. During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. The LTC4300A-3 provides level translation between 3.3V and 5V supplies. The backplane and card can both be powered with supplies ranging from 2.7V to 5.5V. The LTC4300A-3 also incorporates a CMOS threshold ENABLE pin which forces the part into a low current mode and isolates the card from the backplane. When driven to VCC, the ENABLE pin sets normal operation. The LTC4300A-3 is available in the MSOP and 3mm x 3mm DFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. I2C is a trademark of Philips Electronics N. V. *Patent pending.
APPLICATIO S
s s s s
Hot Board Insertion Servers Capacitance Buffer/Bus Extender Desktop Computer
TYPICAL APPLICATIO
VCC 3.3V 0.01F 10k 10k 3 8 1
VCC2 0.01F 10k 2 10k
OUTPUT SIDE 50pF 0.5V/DIV
Input-Output Connection
SCLIN
SCLOUT
SDAIN
6
7
SDAOUT
5 OFF ON
LTC4300A-3 ENABLE GND 4
4300A-3 TA01
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INPUT SIDE 150pF 200ns/DIV
4300A TA02
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LTC4300A-3
ABSOLUTE
AXI U RATI GS
VCC to GND .................................................... - 0.3 to 7V VCC2 to GND .................................................. - 0.3 to 7V SDAIN, SCLIN, SDAOUT, SCLOUT ................. - 0.3 to 7V ENABLE ......................................................... - 0.3 to 7V Operating Temperature Range LTC4300A-3C ......................................... 0C to 70C LTC4300A-3I ...................................... - 40C to 85C
PACKAGE/ORDER I FOR ATIO
TOP VIEW VCC2 1 SCLOUT 2 SCLIN 3 GND 4 9 8 7 6 5 VCC SDAOUT SDAIN ENABLE
ORDER PART NUMBER LTC4300A-3CDD LTC4300A-3IDD DD PART MARKING* LBHG LBHG
TOP VIEW VCC2 SCLOUT SCLIN GND 1 2 3 4 8 7 6 5 VCC SDAOUT SDAIN ENABLE
DD PACKAGE 8-LEAD (3mm x 3mm) PLASTIC DFN
TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 9) PCB CONNECTION IS OPTIONAL
Consult LTC marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
The q denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER Power Supply VCC VCC2 ISD IVCC1 IVCC2 VPRE tIDLE VEN VDIS IEN tPHL tPLH Positive Supply Voltage Card Side Supply Voltage Supply Current in Shutdown Mode VCC Supply Current VCC2 Supply Current Precharge Voltage Bus Idle Time ENABLE Threshold Voltage Disable Threshold Voltage ENABLE Input Current ENABLE Delay, On-Off ENABLE Delay, Off-On ENABLE Pin ENABLE from 0V to VCC 0.1 * VCC VENABLE = 0V VSDAIN = VSCLIN = 0V, VCC1 = VCC2 = 5.5V VSDAOUT = VSCLOUT = 0V, VCC1 = VCC2 = 5.5V SDA, SCL Floating
q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
Start-Up Circuitry 0.8 50 1.0 95 0.5 * VCC 0.5 * VCC 0.1 10 95 1 1.2 150 0.9 * VCC V s V V A ns s
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(Note 1)
Storage Temperature Range MSOP ............................................... - 65C to 150C DFN .................................................. - 65C to 125C Lead Temperature (Soldering, 10 sec) MSOP Only ....................................................... 300C
ORDER PART NUMBER LTC4300A-3CMS8 LTC4300A-3IMS8 MS8 PART MARKING LTBHD LTBHF
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 200C/W
MIN 2.7 2.7
TYP
MAX 5.5 5.5
UNITS V V A mA mA
20 3 2.1 4.1 2.9
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LTC4300A-3
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Rise-Time Accelerators IPULLUPAC Transient Boosted Pull-Up Current Input-Output Connection VOS fSCL, SDA CIN VOL ILEAK fI2C tBUF thD,STA tsu,STA tsu,STO thD, DAT tsu, DAT tLOW tHIGH tf tr Input-Output Offset Voltage Operating Frequency Digital Input Capacitance Output Low Voltage, Input = 0V Input Leakage Current I2C Operating Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock, Data Fall Time Clock, Data Rise Time
The q denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted.
CONDITIONS Positive Transition on SDA, SCL, VCC = 2.7V, VCC2 = 2.7V, Slew Rate = 1.25V/s (Note 2) 10k to VCC on SDA, SCL, VCC = 3.3V (Note 3), VCC2 = 3.3V, VIN = 0.2V Guaranteed by Design, Not Subject to Test Guaranteed by Design, Not Subject to Test SDA, SCL Pins, ISINK = 3mA, VCC = 2.7V, VCC2 = 2.7V SDA, SCL Pins = VCC = 5.5V, VCC2 = 5.5V (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Notes 4, 5) (Notes 4, 5) 0 1.3 0.6 0.6 0.6 300 100 1.3 0.6 20 + 0.1 * CB 20 + 0.1 * CB Note 4: Guaranteed by design, not subject to test. Note 5: CB = total capacitance of one bus line in pF. 300 300
q q
MIN 1
TYP 2
MAX
UNITS mA
0 0 0
100
175 400 10 0.4 5 400
mV kHz pF V A kHz s s s s ns ns s s ns ns
Timing Characteristics
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section. Note 3: The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pullup resistor and VCC voltage is shown in the Typical Performance Characteristics section.
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LTC4300A-3 TYPICAL PERFOR A CE CHARACTERISTICS
ICC vs Temperature
5.3 5.2 5.1 5.0 ICC (mA)
t PHL (ns)
VCC = 5.5V 80
4.9 4.8 4.7 4.6 4.5 4.4 4.3 -50 -25 0 25 50 TEMPERATURE (C) 75 100 VCC = 2.7V
60
IPULLUPAC (mA)
Connection Circuitry VOUT - VIN
300 250
VOUT - VIN (mV)
200 150 VCC = 5V 100 VCC = 3.3V 50 0
5 0 -50
ISD (A)
0
10,000
4
UW
4300-3 G01
Input-Output High to Low Propagation Delay vs Temperature
100 VCC = 2.7V 10 VCC = 3.3V 8 6 4 2 12
IPULLUPAC vs Temperature
VCC = 5V
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VCC = 5.5V
VCC = 3V
20 CIN = COUT = 100pF RPULLUPIN = RPULLUPOUT = 10k 0 -50 -25 0 25 50 TEMPERATURE (C) 75 100
VCC = 2.7V 0 -50 -25 0 25 50 TEMPERATURE (C) 75 100
4300-3 G02
4300-3 G03
ISD vs Temperature
35 30 VCC = 5.5V 25 20 15 10 VCC = 2.7V
TA = 25C VIN = 0V
20,000 30,000 RPULLUP ()
40,000
4300-3 G04
-25
50 25 0 TEMPERATURE (C)
75
100
4300A G05
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LTC4300A-3
PI FU CTIO S
VCC2 (Pin 1): Card Supply Voltage. This is the supply voltage for the devices on the card I2C busses. Connect pull-up resistors from SDAOUT and SCLOUT to this pin. Place a bypass capacitor of at least 0.01F close to this pin for best results. SCLOUT (Pin 2): Serial Clock Output. Connect this pin to the SCL bus on the card. SCLIN (Pin 3): Serial Clock Input. Connect this pin to the SCL bus on the backplane. GND (Pin 4): Device Ground. Connect this pin to a ground plane for best results. ENABLE (Pin 5): Digital CMOS Threshold Input. Grounding this pin puts the part in a low current mode. It also disables the rise-time accelerators, disables the bus discharge circuitry, isolates SDAIN from SDOUT and isolates SCLIN from SCLOUT. For active operation, drive this pin to VCC. If this feature is unused, tie to VCC. Since ENABLE is VCC referenced, do not connect to VCC2 or pull up to VCC2. SDAIN (Pin 6): Serial Data Input. Connect this pin to the SDA bus on the backplane. SDAOUT (Pin 7): Serial Data Output. Connect this pin to the SDA bus on the card. VCC (Pin 8): Main Input Power Supply from Backplane. This is the supply voltage for the devices on the backplane I2C busses. Connect pull-up resistors from SDAIN and SCLIN (and also from SDAOUT and SCLOUT for the LTC4300A-3) to this pin. Place a bypass capacitor of at least 0.01F close to this pin for best results. Exposed Pad (Pin 9, DFN Package Only): Exposed Pad may by be left open or connected to device ground.
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LTC4300A-3
BLOCK DIAGRA
VCC 8
SDAIN 6
SCLIN 3
+ -
STOP BIT AND BUS IDLE 0.5A
+
0.55VCC/ 0.45VCC
-
95s DELAY, RISING ONLY
UVLO ENABLE 5
6
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2-Wire Bus Buffer and Hot SwapTM Controller
2mA SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT CONNECT CONNECT 2mA SLEW RATE DETECTOR 1 VCC2 7 4 SDAOUT 100k 1V PRECHARGE 100k 100k 100k 2mA SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT CONNECT 2mA SLEW RATE DETECTOR 2 SCLOUT
+ -
VCC2 - 1V
+ -
20pF CONNECT CONNECT RD QB S 4 GND 0.5pF
4300A-3 BD
Hot Swap is a trademark of Linear Technology Corporation.
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LTC4300A-3
OPERATIO
Start-Up When the LTC4300A-3 first receives power on its VCC pin, either during power-up or during live insertion, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until VCC rises above 2.5V. The part also waits for VCC2 to rise above 2V. This ensures that the part does not try to function until it has enough voltage to do so. During this time, the 1V precharge circuitry is also active and forces 1V through 100k nominal resistors to the SDA and SCL pins. Because the I/O card is being plugged into a live backplane, the voltage on the backplane SDA and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the worst-case voltage differential these pins will see at the moment of connection, therefore minimizing the amount of disturbance caused by the I/O card. Once the LTC4300A-3 comes out of UVLO, it assumes that SDAIN and SCLIN have been inserted into a live system and that SDAOUT and SCLOUT are being powered up at the same time as itself. Therefore, it looks for either a stop bit or bus idle condition on the backplane side to indicate the completion of a data transaction. When either one occurs, the part also verifies that both the SDAOUT and SCLOUT voltages are high. When all of these conditions are met, the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with those on the backplane, and the rise time accelerators are enabled. Connection Circuitry Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages being low. For proper operation, logic low input voltages should be no higher than 0.4V with respect to the ground pin voltage of the LTC4300A-3. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the LTC4300A-3.
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Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and card capacitances isolated. Because of this isolation, the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms, as described here. Input to Output Offset Voltage When a logic low voltage, VLOW1, is driven on any of the LTC4300A-3's data or clock pins, the LTC4300A-3 regulates the voltage on the other side of the part (call it VLOW2) to a slightly higher voltage, as directed by the following equation (typical): VLOW2 = VLOW1 + 75mV + (VCC/R) * 70 [] where R is the bus pull-up resistance in ohms. For example, if a device is forcing SDAOUT to 10mV where VCC = 3.3V and the pull-up resistor R on SDAIN is 10k, then the voltage on SDAIN = 10mV + 75mV + (3.3/10000) * 70 = 108mV (typical). See the Typical Performance Characteristics section for curves showing the offset voltage as a function of VCC and R. Propagation Delays During a rising edge, the rise-time on each side is determined by the combined pull-up current of the LTC4300A3 boost current and the bus resistor and the equivalent capacitance on the line. If the pull-up currents are the same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure 1 for VCC = VCC2 = 3.3V and a 10k pull-up resistor on each side (50pF on one side and 150pF on the other). Since the output side has less capacitance than the input, it rises faster and the effective propagation delay is negative. There is a finite propagation delay through the connection circuitry for falling waveforms. Figure 2 shows the falling edge waveforms for the same VCC, pull-up resistors and equivalent capacitance conditions as used in Figure 1. An external NMOS device pulls down the voltage on the side with 150pF capacitance; the LTC4300A-3 pulls down the voltage on the opposite side, with a delay of 55ns. This delay is always positive and is a function of supply voltage,
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LTC4300A-3
OPERATIO
OUTPUT SIDE 50pF 0.5V/DIV
Figure 1. Input-Output Connection Low to High Transition
temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows tPHL as a function of temperature and voltage for 10k pull-up resistors and 100pF equivalent capacitance on both sides of the part. By comparison with Figure 2, the VCC = VCC2 = 3.3V curve shows that increasing the capacitance from 50pF to 100pF results in a propagation delay increase from 55ns to 75ns. Larger output capacitances translate to longer delays (up to 150ns). Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. Rise-Time Accelerators Once connection has been established, rise-time accelerator circuits on all four SDA and SCL pins are activated. These allow the user to choose weaker DC pull-up currents on the bus, reducing power consumption while still meeting system rise-time requirements. During positive bus transitions, the LTC4300A-3 switches in 2mA (typical) of current to quickly slew the SDA and SCL lines once their DC voltages exceed 0.6V. Using a general rule of 20pF of capacitance for every device on the bus (10pF for the device and 10pF for interconnect), choose a pull-up current so that the bus will rise on its own at a rate of at least 1.25V/s to guarantee activation of the accelerators.
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INPUT SIDE 150pF INPUT SIDE 150pF 0.5V/DIV OUTPUT SIDE 50pF 200ns/DIV
4300A-3 F01
200ns/DIV
4300A-3 F02
Figure 2. Input-Output Connection High to Low Transition
For example, assume an SMBus system with VCC = 3V, a 10k pull-up resistor and equivalent bus capacitance of 200pF. The rise-time of an SMBus system is calculated from (VIL(MAX) - 0.15V) to (VIH(MIN) + 0.15V), or 0.65V to 2.25V. It takes an RC circuit 0.92 time constants to traverse this voltage for a 3V supply; in this case, 0.92 * (10k * 200pF) = 1.84s. Thus, the system exceeds the maximum allowed rise-time of 1s by 84%. However, using the rise-time accelerators, which are activated at a DC threshold of below 0.65V, the worst-case rise-time is: (2.25V - 0.65V) * 200pF/1mA = 320ns, which meets the 1s rise-time requirement. ENABLE Low Current Disable Grounding the ENABLE pin disconnects the backplane side from the card side, disables the rise-time accelerators, disables the bus precharge circuitry and puts the part in a near-zero current state. When the pin voltage is driven all the way to VCC, the part waits for data transactions on both the backplane and card sides to be complete (as described in the Start-Up section) before reconnecting the two sides.
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LTC4300A-3
APPLICATIO S I FOR ATIO
Resistor Pull-Up Value Selection
The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25V/s on the SDA and SCL pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value R using the formula: R (VCC(MIN) - 0.6)(800,000)/C where R is the pull-up resistor value in ohms, VCC(MIN) is the minimum VCC voltage and C is the equivalent bus capacitance in picofarads (pF). In addition, regardless of the bus capacitance, always choose R 16k for VCC = 5.5V maximum, R 24k for VCC = 3.6V maximum. The start-up circuitry requires logic high voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage.
BACKPLANE CONNECTOR
BACKPLANE VCC2 R7 10k VCC SDA SCL R8 10k
ENA1
ENA2
Figure 3. The LTC4300A-3 in a PCI Application Where All the Pins Have the Same Length. ENABLE Should be Held Low Until All Transients Associated with the Live Insertion Have Settled
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Live Insertion and Capacitance Buffering Application Figures 3 and 4 illustrate the usage of the LTC4300A-3 in applications that take advantage of both its Hot Swap controlling and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise- and fall-time requirements difficult to meet. Placing a LTC4300A-3 on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the LTC4300A-3 drives the capacitance of everything on the card and the backplane must drive only the capacitance of the LTC4300A-3, which is less than 10pF.
I/O PERIPHERAL CARD 1 C1 0.01F VCC SDAIN SCLIN C2 0.01F VCC2 LTC4300A-3 GND SDAOUT SCLOUT ENABLE R3 10k R1 10k R2 10k CARD_SDA CARD_SCL I/O PERIPHERAL CARD 2 C3 0.01F VCC SDAIN SCLIN C4 0.01F VCC2 LTC4300A-3 GND SDAOUT SCLOUT ENABLE R6 10k R4 10k R5 10k CARD2_SDA CARD2_SCL
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LTC4300A-3
APPLICATIO S I FOR ATIO
BACKPLANE VCC2 BACKPLANE CONNECTOR
STAGGERED CONNECTOR
R7 10k VCC SDA SCL ENA1
R8 10k
STAGGERED CONNECTOR
ENA2
Figure 4. The LTC4300A-3 in a Custom Application. Making ENABLE the Shortest Pin Ensures that VCC and VCC2 Connect Before ENABLE is Allowed to Go High, Connecting the Card to the Backplane
5V to 3.3V Level Translator and Power Supply Redundancy Systems requiring different supply voltages for the backplane side and the card side can use the LTC4300A-3, as shown in Figure 5. The pull-up resistors on the card side connect from SDAOUT to SCLOUT to VCC2, and those on the backplane side connect from SDAIN and SCLIN to VCC. The LTC4300A-3 functions for voltages ranging from 2.7V to 5.5V on both VCC and VCC2. There is no constraint on the
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I/O PERIPHERAL CARD 1 C1 0.01F VCC SDAIN SCLIN C2 0.01F VCC2 LTC4300A-3 GND SDAOUT SCLOUT ENABLE R3 10k R1 10k R2 10k CARD_SDA CARD_SCL I/O PERIPHERAL CARD 2 C3 0.01F VCC SDAIN SCLIN C4 0.01F VCC2 LTC4300A-3 GND SDAOUT SCLOUT ENABLE R6 10k R4 10k R5 10k CARD2_SDA CARD2_SCL
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voltage magnitudes of VCC and VCC2 with respect to each other. This application also provides power supply redundancy. If the VCC2 voltage falls below its UVLO threshold, the LTC4300A-3 disconnects the backplane from the card, so that the backplane can continue to function. If the VCC voltage falls below its UVLO threshold and the VCC2 voltage remains active, hold ENABLE at ground to ensure proper operation.
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LTC4300A-3
PACKAGE DESCRIPTION
DD Package 8-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115 TYP 5 0.675 0.05 0.38 0.10 8
3.5 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6)
0.889 0.127 (.035 .005) GAUGE PLANE 5.23 (.206) MIN 3.20 - 3.45 (.126 - .136)
0.42 0.038 (.0165 .0015) TYP
0.65 (.0256) BSC
RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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3.00 0.10 (4 SIDES)
1.65 0.10 (2 SIDES)
(DD8) DFN 1203
0.200 REF
0.75 0.05
4 0.25 0.05 2.38 0.10 (2 SIDES)
1 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 0.102 (.118 .004) (NOTE 3)
8
7 65
0.52 (.0205) REF
0.254 (.010)
DETAIL "A" 0 - 6 TYP
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE
1 1.10 (.043) MAX
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4 0.86 (.034) REF
0.22 - 0.38 (.009 - .015) TYP
0.65 (.0256) BSC
0.127 0.076 (.005 .003)
MSOP (MS8) 0204
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LTC4300A-3
TYPICAL APPLICATIO S
VCC 5V R1 10k SDA SCL R4 10k C2 0.01F SDAIN SCLIN VCC VCC2 C1 0.01F SDAOUT SCLOUT
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RELATED PARTS
PART NUMBER LTC1380/LTC1393 LTC1427-50 LTC1623 LTC1663 LTC1694/LTC1694-1 LT1786F LTC1695 LTC1840 DESCRIPTION Single-Ended 8-Channel/Differential 4-Channel Analog Mux with SMBus Interface Micropower, 10-Bit Current Output DAC with SMBus Interface Dual High Side Switch Controller with SMBus Interface SMBus Interface 10-Bit Rail-to-Rail Micropower DAC SMBus Accelerator SMBus Controlled CCFL Switching Regulator SMBus/I2C Fan Speed Controller in ThinSOTTM Dual I2C Fan Speed Controller COMMENTS Low RON: 35 Single-Ended/70 Differential, Expandable to 32 Single or 16 Differential Channels Precision 50A 2.5% Tolerance Over Temperature, 4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale 8 Selectable Addresses/16-Channel Capability DNL < 0.75LSB Max, 5-Lead SOT-23 Package Improved SMBus/I2C Rise-Time, Ensures Data Integrity with Multiple SMBus/I2C Devices 1.25A, 200kHz, Floating or Grounded Lamp Configurations 0.75 PMOS 180mA Regulator, 6-Bit DAC Two 100A 8-Bit DACs, Two Tach Inputs, Four GPI0 Preserves Data integrity Under Hot Swap Conditions, Provides Capacitive Buffering, Rise-Time Acceleration Provides Capacitive Buffer, 3.3V to 5V Level Translation with Only the Card Bus VCC Supply Level Translators, 1V Signals to Standard 3.3V and 5V Logic Rails Provides Capacitive Buffering, Rise-Time Acceleration, and Input to Output Connection Control Using 2-Wire Bus Commands
LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer LTC4301 LTC4301L LTC4302-1/LTC4302-2 Supply Independent 2-Wire Bus Buffer Hot-Swappable 2-Wire Bus Buffer with Low Voltage Level Translation Addressable I2C and SMBus Compatible Bus Buffers
ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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CARD_VCC, 3.3V R3 10k R2 10k CARD_SDA CARD_SCL
LTC4300A-3 GND
ENABLE
Figure 5. 5V to 3.3V Level Translator
4300a3f LT/TP 0404 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

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